For today I am grabbing a newer board that has not been fully checked out yet; an Altera Max V device. I have stuffed the CPLD, the clock oscillator, some LED’s and part of the onboard power ...

Using an external MCU as a crude clock source for the Altera CPLD. (Credit: [Doug Brown]) One exciting feature of hardware development involving MCUs and FPGAs is that you all too often need ...

Details on Altera’s performance leadership ... automated way to optimize power consumption in FPGA, CPLD, and structured ASIC designs. In addition to the new PowerPlay technology, version 4.2 also ...

San Jose, Calif., May 9, 2011—Altera Corporation (Nasdaq: ALTR) today announced the release of its Quartus ® II software version 11.0, the industry’s number one software in performance and ...