Electronic Design

A Methodology to Speed DFT Signoff

Shipping high-quality ICs requires that design-for-test (DFT) methodologies be included in a design. DFT provides external access at the device’s I/O pins to internal registers to either control or ...
Semiconductor Engineering

Packetized Scan Test

Bus-based packetized scan data decouples test delivery and core-level DFT requirements so core-level compression configuration can be defined completely independently of chip I/O limitations. Grouping ...
Electronic Design

Design-For-Test The Smart Way: dFT With A "Big T" And A "Little d"

Design-for-test, or DFT, should facilitate high-quality test, not change the design. Test techniques and strategies need to supply a high-quality test that screens out defective devices, avoiding ...
EDN

Successful ASIC test requires cooperation

With increasing numbers of ASICs finding their way into high-volume products, production testing of these devices must be fast, complete, trouble-free, and economical. To achieve these goals, ...
EDN

First STIL link between DFT and production test for SoC

Design-for-test (DFT) software maker Teseda (Portland, Oregon) and test-and-measurement house Agilent Technologies (Palo Alto, Calif.) announce a link that both companies claim will ensure, for the ...