The Bitec Camera Front End IP allows developers to interface CMOS and CCD cameras to an Altera FPGA. Using a memory optimised line buffer, the core sits between a backend SoPC and the raw camera ...

The IP Core may be used in either the BASE, MEDIUM or FULL configurations as defined in the Camera Link specification. In general, each data lane can support around 500 Mbps per LVDS lane on basic ...

Or in [ultraembedded’s] case, take a custom FPGA player from 800 x 600 to 1280 x 720. The hardware used is a Digilent Arty A7 and PMOD boards ... a FAT32 interface, an IR decoder, and a UI ...