The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. To ...

This post addresses the specific hurdle of effective and efficient manufacturing tests for these complex devices. It outlines ...

Yield improvement at sub 100-nm technologies relies on the latest scan test techniques. As IC feature sizes shrink below 90 nm, in-line inspection techniques to determine yield-limiting problems ...

Scan technology was developed as a structured test technique that divided the complex sequential nature of a design into small combinational logic blocks that could be tested individually. This added ...