EDN

SystemVerilog reference verification methodology: Introduction

Verification is the single biggest challenge in the design of system-on-chip (SoC) devices and reusable IP blocks. Traditional verification methods struggle to keep pace with the ever-increasing size ...
EDN

Synopsys announces SystemVerilog testbench

At the SNUG (Synopsys Users Group) East meeting this week in Boston, Synopsys will release Pioneer-NTB, its new automatic testbench-verification system supporting the SystemVerilog design and ...
Design-Reuse

Synopsys Advances VCS Solution by Adding Assertion IP Library and Native Testbench Support for SystemVerilog

Latest version of the VCS® solution speeds standards-based verification by unifying SystemVerilog and SystemCâ„¢ languages in a single tool MOUNTAIN VIEW, Calif., May 31, 2005-- Synopsys, Inc. (Nasdaq ...