Abstract: This article presents an ultra-low-power D flip-flop (FF) named clock-load reduced FF (CRFF), which employs 23 transistors with only three clock load transistors to support fully static, ...
Abstract: In this work, we introduce a novel low-power flipflop design. The FF is a single-bit memory component that is both synchronous and bi-stable. Here, we apply a pseudo-MOS approach, together ...
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