IEEE

1800-2017 - IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language

Abstract: The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes ...
IEEE

HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers

Abstract: Recently, the use of large language models (LLMs) for Verilog code generation has attracted great research interest to enable hardware design automation. However, previous works have shown a ...
GitHub

Colab tutorials for Coral

These Jupyter notebooks provide interactive Python tutorials for development with Coral. You can download these files and run them on a local Jupyter notebook, but ...
GitHub

Tutorial on the setup and simulation of a membrane protein with AMBER Lipid21 and PACKMOL-Memgen

Disclaimer: I hope this tutorial will be useful to others wishing to run molecular dynamics simulations of membrane proteins with AMBER. However, it is as much for my own reference as a guide to ...